1. Field
The present disclosure pertains to register renaming techniques.
2. Description of Related Art
Computer programs often make extensive use of registers in performing desired operations. Managing registers efficiently is one great challenge for an instruction processor. Techniques which allow more efficient management of register resources may be beneficial to overall processing efficiency and therefore quite desirable.
Register renaming is one technique that allows greater throughput with a relatively limited register set. In a processor performing register renaming, multiple copies of a single register may be active at different states of commitment and/or speculation at a single time. As instructions retire, the committed state of the registers are updated in some form of register map which keeps track of the renamed registers.
In one prior art register renaming technique, a pool of registers with a free list is maintained. When a new register is needed, it is allocated from the free list, and a pointer to the register is tracked appropriately. In a multithreading microprocessor, the different threads typically each maintain their own pointers to the accurate register values. However, each pointer for a register points to an accurate value with respect to a different thread. Pointers are thread specific and a pointer associated with one thread should not point to an accurate value intended to be used by a different thread. For example, see Prior Art Table 1. In this prior art technique physical pointer 0 for each register corresponds to a first thread, and physical pointer 1 for each register corresponds to a second thread.
PRIOR ART TABLE 1ArchitectedRegisterPhysical Pointer - Thread 0Physical Pointer - Thread 1R0P4P12R1P2P35. . .. . .. . .R7P247P20
Eager execution is a known technique which attempts to hide branch prediction latencies by executing both paths of a branch in separate threads. Eager execution complicates register renaming because another copy of the processor state is needed when a branch forks. Prior art approaches suggest copying over and maintaining a new set of registers dedicated to the forked thread that executes the second path. Then, when the branch is finally resolved, the extra registers (or their map values) may be copied over to establish the correct machine state. Such an approach may be costly due to the hardware and/or time necessary to allocate and track extra registers, as well as the hardware and/or time necessary to copy the extra registers back into a non-speculative map.